1. Field of the Invention
The invention relates to a signal sampling system which is self-aligning. In its more particular aspects the present invention relates to such a system which includes a clock input for receiving a system clock signal, an adjustable delay line which is coupled to the clock input and which comprises tapping points for tapping delayed clock signals, a sampling circuit having clock inputs for receiving the system clock signal and the delayed clock signals and at least one signal input for receiving at least one signal to be sampled, and adjusting means for adjusting the delay line so that equidistant sampling instants are obtained.
The invention also relates to a logic analyser comprising a number of input channels for receiving digital signals.
2. Description of the Related Art
A logic analyser is an instrument for collecting and tracking groups of digital signals in order to test the operation of a digital system such as a microprocesor system. A large number of digital signals are collected and information regarding the digital signals is displayed on a display screen, for example as logic values "1" and "0" or as a time sequence diagram with high-low signal representation. The logic analyser may be a stand-alone instrument or may be combined with another apparatus such as a digital storage oscilloscope or a pattern generator; it may also be included as an instrument-on-card in a system. Generally, a logic analsyser will be suitable for executing so-called state analysis as well as timing analysis. In the case of timing analysis, signal transitions from "0" to "1" and "1" to "0" are observed in a time sequence diagram in which a number of digital signals are represented. In the case of logic timing analysis, digital signals of a digital system to be tested are asynchronously sampled, the resolution being determined by the sampling frequency.
U.S. patent Specification No. 4,763,105 discloses a self-aligning sampling system for the sampling of signals, comprising a clock input for receiving a system clock signal, an adjustable delay line which is coupled to the clock input and which comprises tapping points for tapping delayed clock signals, a sampling circuit comprising clock inputs for receiving the system clock signal and the delayed clock signals and a signal input for receiving a signal to be sampled, adjusting means for adjusting the delay line so that equidistant sampling instants are obtained, and programmed arithmetic means for generating adjusting signals for the adjusting means. It concerns a sampling system for inter alia digital storage oscilloscopes in which a number of sampling circuits operate in parallel in order to achieve a high effective sampling frequency. Each sampling circuit thereof is supplied with a clock signal derived from a system clock signal. The clock signals are tapped from a delay line. In a data acquisition memory sampling values of an in this case analog signal are stored in an interleaved fashion. In order to obtain sampling instants which are as equidistant as possible, the delay line is rendered adjustable. The delay line is calibrated via an automatic calibration procedure during which a sinusoidal voltage of known amplitude and frequency is presented to the sampling system as a calibration signal. The calibration procedure is executed by means of programmed arithmetic means and essentially comprises the following steps. M sampling circuits which comprise analog-to-digital converters, for example M=6, and which are coupled to the delay line, take I samples, for example I=16. The I.M samples of the analog calibration signal are stored as data in an acquisition memory. From the data set of I.M samples, being weighted first using a Blackman-Harris window, a frequency spectrum is determined by Fourier transformation, this frequency spectrum is used to derive a further complex data set containing peak information of the frequency spectrum. The complex data set is subjected to inverse Fourier transformation and from the resultant complex data set in the time domain phase information representative of an incorrectly adjusted delay line is derived. The delay line sections are adjusted on the basis of this phase information. The calibration procedure followed is complex and intricate and, moreover, is suitable only for analog sampling systems.